In order to test integrated circuits effectively it is known to provide diagnostic features on the circuit such as scan cells. Scan cells allow scan testing of the circuit to be performed which allows for the control and observation of state elements within the integrated circuit. Scan cells are generally provided in association with flip-flops or latches on the circuit by adding a scan cell capability to the design whereby a signal value may be captured and then serially scanned out of the circuit for diagnostic purposes.
Providing flip flops with a scan cell capability can be done in a number of ways. A common way is to provide a multiplexed flip-flop, which has a multiplexer on its input and output which can select between data and scan inputs in response to a control signal (scan enable). FIG. 1 shows such a multiplexed D flop 10 according to the prior art.
This flop comprises data and scan inputs 22 and 32 respectively. These inputs comprise respective tristatable devices 24 and 34 controlled by the scan enable signal. Thus, if scan is enabled, data input 22 is isolated from forward data path 25 running from data input 22 to data output 29, while if scan is not enabled, scan input 32 is isolated by tristate device 34 from the forward data path 25. The multiplexed D flop is otherwise a standard flop with a transmission gate 23 between the input 22 and master latch 26 and a transmission gate 27 between the master latch 26 and slave latch 28. At the output end, there is a data output 29 and a scan output 39, the scan output being enabled by the scan enable signal. The behaviour of the flop is thus, controlled by the state of the scan enable se input. If se is high, then the flop is in shift mode and the data can be scanned though the flop via the scan input 32 and scan output 39 ports. If se is low, then the flop is in functional mode and behaves as a normal master slave flop. In both states the clock clk input is used to update the state of the flop.
The advantage of the design of the mux-D flop of FIG. 1 is that it allows for scan by simply providing a 2-input multiplexer at the input, an extra logic gate at the output and an extra control signal. Thus, the increase in circuit area required for this design is small. A disadvantage of the design is that the multiplexer impacts the functional path performance. Furthermore, clocked scan flip flops are more suited to high speed operation and generally provide lower power consumption than the Mux-D flip-flop designs.
Clocked-scan and LSSD are other well known techniques that allow for scan. These do not have the performance impact of the multiplexer on the functional path. However, they increase the area of the multiplexer by adding an additional latch and some extra clock inputs. Thus, circuit area is typically increased by 30-50% compared to the mux-D approach.
FIG. 2 shows a 3 latch clocked scan flop according to the prior art. As can be seen the functional path between data input 22 and data output 29 is unaffected by this design, thus, functional operation is good. However, this is at a cost of circuit area, in this design and additional latch and an additional scan clock signal have been provided. This gives and increase in area of approximately 33% compared to the mux-D approach.
U.S. Pat. No. 6,380,780 addressed the problem of scan flip-flop designs either increasing area by a large amount or reducing performance and proposes a design having only two latches, but having additional transistors. The design has the drawback of requiring at least four control or clock signals to affect the correct functionality.